m65608e rev. e ? june 5, 2000 1 introduction the m65608e is a very low power cmos static ram organized as 131072 8 bits. temic brings the solution to applications where fast computing is as mandatory as low consumption, such as aerospace electronics, portable instruments, or embarked systems. utilizing an array of six transistors (6t) memory cells, the m65608e combines an extremely low standby supply current (typical value = 0.2 a) with a fast access time at 30 ns over the full military temperature range. the high stability of the 6t cell provides excellent protection against soft errors due to noise. the m65608e is processed according to the methods of the latest revision of the mil std 883 (class b or s), esa scc 9000 or qml. features access time: 30, 45 ns very low power consumption active : 250 mw (typ) standby : 1 w (typ) data retention : 0.5 w (typ) wide temperature range : ?55 to +125 c 400 mils width package ttl compatible inputs and outputs asynchronous single 5 volt supply equal cycle and access time gated inputs : no pull-up/down resistors are required interface block diagram 128 k 8 very low power cmos sram rad tolerant
m65608e rev. e ? june 5, 2000 2 pin configuration 32 pins dil side-brazed 400 mils 32 pins flatpack 400 mils pin names a0 ? a16 address inputs i/o0 ? i/o7 data input/output cs 1 chip select 1 cs 2 chip select 2 w write enable oe output enable v cc power gnd ground truth table cs 1 cs 2 w oe inputs/ outputs mode h x x x z deselect/ power-down x l x x z deselect/ power down l h h l data out read l h l x data in write l h h h z output disable l = low, h = high, x = h or l, z = high impedance.
m65608e rev. e ? june 5, 2000 3 electrical characteristics absolute maximum ratings supply voltage to gnd potential : - 0.5 v + 7.0 v . . . . . . . . . . . . . . . dc input voltage : gnd ? 0,3 v to vcc + 0,3 . . . . . . . . . . . . . . . . . dc output voltage high z state : gnd ? 0,3 v to vcc + 0,3 . . . . . . storage temperature : ? 65 c to + 150 c . . . . . . . . . . . . . . . . . . . . . . output current into outputs (low) : 20 ma . . . . . . . . . . . . . . . . . . . . . . electro statics discharge voltage : > 2 001 v . . . . . . . . . . . . . . . . . . . (mil std 883d method 3015.3) operating range operating voltage operating temperature military 5 v 10 % ? 55 c to + 125 c recommended dc operating conditions parameter description minimum typical maximum unit vcc supply voltage 4.5 5.0 5.5 v gnd ground 0.0 0.0 0.0 v vil input low voltage gnd ? 0.3 0.0 0.8 v vih input high voltage 2.2 ? v cc + 0.3 v capacitance parameter description minimum typical maximum unit cin (1) input low voltage ? ? 8 pf cout (1) output high volt ? ? 8 pf note : 1. guaranteed but not tested. dc parameters parameter description minimum typical maximum unit iix (2) input leakage current ? 1 ? 1 a ioz (2) output leakage current ? 1 ? 1 a vol (3) output low voltage ? ? 0.4 v voh (4) output high voltage 2.4 ? ? notes : 2. gnd < vin < vcc, gnd < vout < vcc output disabled. 3. vcc min. iol = 8.0 ma. 4. vcc min. ioh = ? 4.0 ma.
m65608e rev. e ? june 5, 2000 4 consumption symbol description 65608 ? 30 65608 ? 45 unit value iccsb (5) standby supply current 2 2 ma max iccsb 1 (6) standby supply current 300 300 a max iccop (7) dynamic operating current 130 100 ma max notes : 5. cs 1 vih or cs 2 vil and cs 1 vil. 6. cs 1 vcc ? 0.3 v or, cs 2 < gnd + 0.3 v and cs 1 0.2 v 7 . f = 1 / tavav, iout = 0 ma, w = oe = vih, vin = gnd/vcc, vcc max. ac parameters input pulse levels : gnd to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise : 5 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input timing reference levels : 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output loading iol/ioh (see figure 1a and 1b) : + 30 pf . . . . . . . . . ac test loads waveforms figure 1a figure 1b figure 2 data retention mode mhs cmos ram ? s are designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules insure data retention : 1. during data retention chip select cs 1 must be held . high within vcc to vcc -0.2 v or, chip select cs 2 must be held low within gnd to gnd + 0.2 v. 2. output enable (oe ) should be held high to keep the ram outputs high impedance, minimizing power dissipation. 3. during power up and power down transitions cs 1 and oe must be kept between vcc + 0.3 v and 70 % of vcc, or with cs 2 between gnd and gnd - 0.3 v. 4. the ram can begin operation > tr ns after vcc reaches the minimum operation voltages (4.5 v).
m65608e rev. e ? june 5, 2000 5 timing data retention characteristics parameter description minimum typical t a = 25 c maximum unit vccdr vcc for data retention 2.0 ? ? v tcdr chip deselect to data retention time 0.0 ? ? ns tr operation recovery time tavav ( 9 ) ? ? ns iccdr1 (10) data retention current @ 2.0 v ? 0.1 150 a iccdr2 (10) data retention current @ 3.0 v ? 0.2 200 a notes : 9 . tavav = read cycle time. 10. cs 1 = vcc or cs 2 = cs 1 = gnd, vin = gnd/vcc, this parameter is only tested at vcc = 2 v.
m65608e rev. e ? june 5, 2000 6 write cycle symbol parameter 65608 ? 30 65608 ? 45 unit value tavaw write cycle time 30 45 ns min tavwl address set-up time 0 0 ns min tavwh address valid to end of write 22 35 ns min tdvwh data set-up time 18 25 ns min te 1 lwh cs 1 low to write end 22 35 ns min te 2 hwh cs 2 high to write end 22 35 ns min twlqz write low to high z (11) 8 15 ns max twlwh write pulse width 22 35 ns min twhax address hold from to end of write 0 0 ns min twhdx data hold time 0 0 ns min twhqx write high to low z (11) 0 0 ns min read cycle symbol parameter 65608 ? 30 65608 ? 45 unit value tavav read cycle time 30 45 ns min tavqv address access time 30 45 ns max tavqx address valid to low z 5 5 ns min te 1 lqv chip-select 1 access time 30 45 ns max te 1 lqx cs 1 low to low z (11) 3 3 ns min te 1 hqz cs 1 high to high z (11) 18 20 ns max te 2 hqv chip-select 2 access time 30 45 ns max te 2 hqx cs 2 high to low z (11) 3 3 ns min te 2 lqz cs 2 low to high z (11) 18 20 ns max tglqv output enable access time 12 15 ns max tglqx oe low to low z (11) 0 0 ns min tghqz oe high to high z (11) 8 15 ns max notes : 11. parameters guaranteed, not tested, with output loading 5 pf. (see fig. 1.b.).
m65608e rev. e ? june 5, 2000 7 write cycle 1. w controlled. oe high during write te1lwh write cycle 2. w controlled. oe low
m65608e rev. e ? june 5, 2000 8 write cycle 3. cs 1 or cs 2 controlled. note : 12. the internal write time of the memory is defined by the overlap of cs 1 low and cs 2 high and w low. both signals must be actived to initiate a write and either signal can terminate a write by going in actived. the data input setup and hold timing s hould be referenced to the actived edge of the signal that terminates the write. data out is high impedance if oe = vih.
m65608e rev. e ? june 5, 2000 9 read cycle nb 1 read cycle nb 2 read cycle nb 3
m65608e rev. e ? june 5, 2000 10 ordering information m = military ? 55 to +125 c s = space ? 55 to +125 c c9 = side brazed 32 pins 400 mils dj = flat package 32 pins 400 mils 0 = die 128k 8 static ram blank = mhs standards /883 = mil-std 883 class b or s sb/sc = scc 9000 level b/c m ? 65608e m dj v 30 ns 45 ns temperature range package device speed flow* ? 45 v = very low power grade /883 * for ordering in qml quality level, use the qml pin according to smd n o 5962 ? 89598. the information contained herein is subject to change without notice. no responsibility is assumed by temic for using this publ ication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use .
|
